Versal Configuration Pins
PMP7977 User's Guide
Versal System Monitor
SystemVerilog Study Notes. AMD Xilinx 7 series FPGAs XADC - Blog - FPGA - element14 Community
Henry Choi: Bare metal code to read ADC on Zynq
Zybo Z7 XADC Aux Analog inputs stuck at 0x5999 and 0x5111 - FPGA - Digilent Forum
ML510 Embedded Dev Platform Datasheet by Xilinx Inc. | Digi-Key Electronics
ML510 Embedded Dev Platform Datasheet by Xilinx Inc. | Digi-Key Electronics
How to constraint the XADC to external pins - FPGA - Digilent Forum
66002 - Virtex UltraScale FPGA VCU108 Evaluation Kit - Rev 1.0 - JTAG chain might become inactive after configuration
How to use VauxN on XADC
XADC constraints and I/O
Adam Taylor's MicroZed Chronicles, Part 107: Combining XADC and Interrupts with Real-World Signals
Xilinx DS202 Virtex-5 FPGA Data Sheet: DC and Switching ...
ZC706 Evaluation Board for the Zynq-7000 XC7Z045 SoC User Guide (UG954)
Use the ZYNQ XADC with DMA part 1: bare metal - Blog - FPGA - element14 Community
How to use VauxN on XADC
DS083: "Virtex-II Pro™ Platform FPGAs: Advance Product Specification"
Using the SYSMON in System Design - Designing with Xilinx FPGAs Using Vivado - FPGAkey
XADC constraints and I/O
FPGA: HSWAP pin - Corelis Boundary-Scan Blog
